
dsPIC30F Flash Programming Specification
DS70102K-page 58
2010 Microchip Technology Inc.
13.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
TABLE 13-1:
AC/DC CHARACTERISTICS
Standard Operating Conditions
(unless otherwise stated)
Operating Temperature: 25
° C is recommended
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
D110
VIHH
High Programming Voltage on MCLR/VPP
9.00
13.25
V
—
D112
IPP
Programming Current on MCLR/VPP
—300
μA—
D113
IDDP
Supply Current during programming
—
30
mA
Row Erase
Program
memory
—
30
mA
Row Erase
Data EEPROM
—
30
mA
Bulk Erase
D001
VDD
Supply voltage
2.5
5.5
V
—
D002
VDDBULK Supply voltage for Bulk Erase
programming
4.5
5.5
V
—
D031
VIL
Input Low Voltage
VSS
0.2 VSS
V—
D041
VIH
Input High Voltage
0.8 VDD
VDD
V—
D080
VOL
Output Low Voltage
—
0.6
V
IOL = 8.5 mA
D090
VOH
Output High Voltage
VDD - 0.7
—
V
IOH = -3.0 mA
D012
CIO
Capacitive Loading on I/O Pin (PGD)
—
50
pF
To meet AC
specifications
P1
TSCLK
Serial Clock (PGC) period
50
—
ns
ICSP mode
1—
μs
Enhanced
ICSP mode
P1a
TSCLKL
Serial Clock (PGC) low time
20
—
ns
ICSP mode
400
—
ns
Enhanced
ICSP mode
P1b
TSCLKH
Serial Clock (PGC) high time
20
—
ns
ICSP mode
400
—
ns
Enhanced
ICSP mode
P2
TSET1
Input Data Setup Timer to PGC
↓
15
—
ns
—
P3
THLD1
Input Data Hold Time from PGC
↓
15
—
ns
—
P4
TDLY1
Delay between 4-bit command and
command operand
20
—
ns
—
P4a
TDLY1a
Delay between 4-bit command operand
and next 4-bit command
20
—
ns
—
P5
TDLY2
Delay between last PGC
↓of command to
first PGC
↑ of VISI output
20
—
ns
—
P6
TSET2VDD
↑ setup time to MCLR/VPP
100
—
ns
—
P7
THLD2
Input data hold time from MCLR/VPP
↑
2—
μs
ICSP mode
5
—
ms
Enhanced
ICSP mode
P8
TDLY3
Delay between last PGC
↓ of command
word to PGD driven
↑ by programming
executive
20
—
μs—
P9a
TDLY4
Programming Executive Command
processing time
10
—
μs—